An Eye on Agilent Test & Measurement

July 12, 2010

Agilent Technologies presents Webcast on Simplified Receiver Test of Retiming Architectures as USB3/SATA

Filed under: J-BERT,Serial ATA,Webcast — janetsmithagilent @ 4:39 pm
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Many of today’s digital interface standards use 8B/10B coding and a concept of inserting or removing filler symbols (Aligns or Skip symbols) to compensate for different clock speeds within the system.

This webcast covers the basics of 8B/10B coding and data re-timing as these concepts are deployed in most common standards. It explains how such receivers are tested with Agilent’s latest J-BERT N4903B. Examples from SATA and USB 3.0 will be used to  illustrate the benefits of the new approach.

When:          Wednesday, July 28, 2010 10:00 a.m. PT / 1:00 p.m. ET

Where:         Register on line at:
http://www.home.agilent.com/agilent/redirector.jspx?action=ref&cname=AGILENT_EDITORIAL&ckey=1908692&cc=US&lc=eng&mcr=true&cmpid=36385

Additional Information: www.agilent.com/find/sata_rsg and  www.agilent.com/find/usb3_rx_test.

Backgrounders about USB and SATA technology and Agilent’s test solutions are available at www.agilent.com/find/usb_backgrounder and www.agilent.com/find/sata_backgrounder.

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April 26, 2010

Behind the scenes: J-BERT Best in Test award

Filed under: Awards,J-BERT,Uncategorized — janetsmithagilent @ 5:00 pm
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How does a company win a Test and Measurement World Best in Test award? And how does it win five Best in Test awards? The answer is technology leadership, and this is one “behind the scenes” story of an award winner.

Winner for the 2010 Best in Test product in the Bit-error-rate testers category, the Agilent J-BERT N4903B owes its success to early and in-depth collaboration with key customers, focusing on their’ leading-edge technological needs for high-speed digital buses used in computer chips. The J-BERT N4903B is a high-performance serial BERT that provides the most complete jitter tolerance test for embedded and forward clocked devices.

R&D engineers sought feedback on product requirements, placed prototypes at customer sites, and visited customers often to help them turn on and test chips while getting feedback during the design phase to optimize features and specifications. In addition, the team worked with standards bodies to understand and implement early requirements. Since its launch in February 2009, no other competitor product offers the value and capability of the J-BERT B and it continues to gain market visibility with awards from Electronic Products 2009 Product of the Year, EDN Hot 100 Electronic Products, finalist in the Design Vision award, and the Best in Test honor.

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